1. Field of the Invention
The present invention generally relates to semiconductor devices, and particularly relates to a semiconductor device equipped with a timing-stabilization circuit such as a DLL (delay-locked loop) circuit.
2. Description of the Related Art
FIG. 1 is a block diagram of a configuration in which a DLL circuit is used as a timing-stabilization circuit for data-input operations.
The configuration of FIG. 1 includes an input buffer 501, a variable-delay circuit 502, a clock-control circuit 503, an input circuit 504, a frequency divider 505, a phase comparator 506, a delay-control circuit 507, a variable-delay circuit 508, a dummy-input circuit 509, a dummy-input buffer 510, and a lock-on detector 511.
A clock signal CLK input to the input buffer 501 is compared with a reference-voltage level Vref, and is output as an internal-clock signal i-clk from the input buffer 501. The internal-clock signal i-clk is delayed by the variable-delay circuit 502 by an appropriate delay amount, and is supplied to the input circuit 504 via the clock-control circuit 503. The input circuit 504 uses the internal-clock signal i-clk as a synchronization signal to latch input data. The latched input data is then supplied from the input circuit 504 to internal circuits of the semiconductor device.
The signal path from the input of the clock signal CLK to the input circuit 504 inevitably introduces a delay which is inherent to the circuit, so that the input data supplied from the input circuit 504 to the internal circuits has a timing displacement relative to the input clock signal CLK. In order to ensure that the input data supplied to the internal circuits is adjusted to have a predetermined timing relation with the clock signal CLK supplied from an external source, a DLL circuit mainly comprised of the phase comparator 506, the delay-control circuit 507, and the variable-delay circuit 508 is employed.
The internal-clock signal i-clk is subjected to frequency division in the frequency divider 505 to generate a dummy-clock signal d-clk and a reference-clock signal c-clk. The dummy-clock signal d-clk is supplied to the variable-delay circuit 508. The variable-delay circuit 508 is controlled to delay the dummy-clock signal d-clk by the same delay amount as that applied by the variable-delay circuit 502. The dummy-clock signal d-clk delayed by the variable-delay circuit 508 is then supplied to the phase comparator 506 via the dummy-input circuit 509 and the dummy-input buffer 510. Here, the dummy-input circuit 509 has the same delay characteristics as the input circuit 504, and the dummy-input buffer 510 has the same delay characteristics as the input buffer 501.
The phase comparator 506 makes a comparison of the reference-clock signal c-clk with the clock signal supplied from the dummy-input buffer 510. To ensure that both clock signals have the same phase, the phase comparator 506 controls the delay amount of the variable-delay circuit 508 via the delay-control circuit 507. In this manner, the clock signal supplied from the dummy-input circuit 509 is adjusted so as to have a predetermined timing relation with the input clock signal CLK.
When the clock-control circuit 503 is ignored, a total delay of the input buffer 501, the variable-delay circuit 502, and the input circuit 504 is equal to a total delay of the dummy-input buffer 510, the variable-delay circuit 508, and the dummy-input circuit 509. Because of this, the input data supplied from the input circuit 504 ends up having the predetermined timing relation with the input clock signal CLK.
In this configuration, even when the characteristics of the input buffer 501, the variable-delay circuit 502, and the input circuit 504 are changed due to variations in a power voltage and/or temperature, the characteristics of the dummy-input buffer 510, the variable-delay circuit 508, and the dummy-input circuit 509 also change in the same manner. Because of this, the input data supplied from the input circuit 504 to the internal circuits always keeps the same timing relation with the input clock signal CLK regardless of a power-voltage variation and/or a temperature variation.
The lock-on detector 511 checks whether the DLL circuits has locked on, based on signals supplied from the phase comparator 506. That is, the lock-on detector 511 checks whether the two clock signals subjected to phase comparison by the phase comparator 506 have the same phase. When a lock-on condition is established, the lock-on detector 511 controls the frequency divider 505 to lower the frequency of the dummy-clock signal d-clk and the reference-clock signal c-clk, thereby reducing power consumption.
The delay-control circuit 507, when set to a maximum delay amount, outputs an overflow signal. Each of the variable-delay circuits 502 and 508 is comprised of a predetermined number of delay elements arranged in series, and is controlled by the delay-control circuit 507. Because of this configuration, the number of usable delay elements is limited in nature. If the delay amount is set to a possible maximum amount, the variable-delay circuits 502 and 508 cannot further increase the delay. In this case, the overflow signal indicating detection of overflow is supplied to the clock-control circuit 503. When overflow is detected, the clock-control circuit 503 selects the internal-clock signal i-clk bypassing the variable-delay circuit 502 rather than selecting the clock signal supplied from the variable-delay circuit 502, and supplies the internal-clock signal i-clk to the input circuit 504.
Clock stabilization using the DLL circuit as described above is employed with respect to not only an input portion of the semiconductor device but also an output portion thereof. In such a case, data-output operations can be conducted at predetermined stable timings.
The configuration of FIG. 1 has a drawback in that overflow cannot be detected outside the semiconductor device. During a test of the semiconductor device, therefore, it is impossible to know whether data is input by using the internal-clock signal i-clk delayed by the variable-delay circuit 502 or by using the internal-clock signal i-clk bypassing the variable-delay circuit 502. This prevents an appropriate test from being carried out in an attempt to learn characteristics of the semiconductor device.
Further, the configuration of FIG. 1 does not take into consideration how to detect overflow when the variable-delay circuits are comprised of a rough-delay circuit and a fine-delay circuit arranged in series or when a plurality of internal clocks are used in the semiconductor device.
Moreover, the configuration of FIG. 1 continues to supply the internal-clock signal i-clk to the variable-delay circuit 502 and to supply the dummy-clock signal d-clk to the variable-delay circuit 508 even after overflow is detected. As previously described, upon detection of overflow, the internal-clock signal i-clk which bypasses the variable-delay circuit 502 will be used as a synchronization signal for the data input. In this case, the delay control by the variable-delay circuit 502 is irrelevant to the operations of the semiconductor device. There is no need, therefore, to supply the internal-clock signal i-clk to the variable-delay circuit 502. Also, there is no need to supply the dummy-clock signal d-clk to the variable-delay circuit 508 such that control of the dummy-clock signal d-clk is carried out at relatively short intervals by the variable-delay circuit 508. Sustained supply of the internal-clock signal i-clk to the variable-delay circuit 502 and of the dummy-clock signal d-clk having a relatively high frequency to the variable-delay circuit 508 results in excessive power consumption.
Accordingly, there is a need for a semiconductor device which allows overflow of a variable-delay circuit in a DLL circuit to be detected outside the semiconductor device.
Also, there is a need for a semiconductor device which detects overflow of variable-delay circuits in DLL circuits when a plurality of internal clocks are used or when a variable-delay circuit is comprised of two stages connected in series.
Further, there is a need for a semiconductor device which can reduce power consumption in a DLL circuit when overflow is detected in a variable-delay circuit of the DLL circuit.
Accordingly, it is a general object of the present invention to provide a semiconductor device which can satisfy the needs described above.
It is another and more specific object of the present invention to provide a semiconductor device which allows overflow of a variable-delay circuit in a DLL circuit to be detected outside the semiconductor device.
It is still another object of the present invention to provide a semiconductor device which detects overflow of variable-delay circuits in DLL circuits when a plurality of internal clocks are used or when a variable-delay circuit is comprised of two stages connected in series.
It is yet another object of the present invention to provide a semiconductor device which can reduce power consumption in a DLL circuit when overflow is detected in a variable-delay circuit of the DLL circuit.
A semiconductor device according to the present invention includes an input buffer buffering an external clock signal to supply an internal clock signal, a timing-stabilization circuit which generates a plurality of phase-adjusted clock signals by adjusting delays of a plurality of variable-delay circuits as the plurality of variable-delay circuits delay the internal clock signal, and an overflow-detection circuit which detects overflow when at least one of the plurality of variable-delay circuits has a delay set to an upper end of an adjustable delay range.
The semiconductor device described above has the timing-stabilization circuit which generates the plurality of phase-adjusted clock signals, where overflow is detected when a delay is set to the upper end of the adjustable delay range in at least one of the variable-delay circuits. An appropriate detection of overflow can thus be made even when the plurality of phase-adjusted clock signals are used.
According to one aspect of the present invention, the overflow is detected at an instance when the delay is set to the upper end or at an instance when the delay is attempted to be increased from the upper end, so that an appropriate overflow detection is achieved.
According to another aspect of the present invention, an overflow-detection signal is output to an exterior of the semiconductor device, so that a check can be made outside the semiconductor device as to whether overflow is present.
According to another aspect of the present invention, a frequency divider is used in the timing-stabilization circuit, and lowers a frequency of frequency-divided clock signals when overflow is detected, thereby suppressing power consumption in the timing-stabilization circuit.
According to another aspect of the present invention, supply of the internal clock signal to the variable-delay circuits is stopped when overflow is detected, thereby avoiding unnecessary power consumption in the variable-delay circuits.
According to another aspect of the present invention, when overflow is detected, the internal clock signal or an inverse of the internal clock signal is supplied to internal circuits as substitutes for the phase-adjusted clock signals serving as synchronization signals in the internal circuits. When a latch is provided as one of the internal circuits, for example, the latch can latch data while securing a sufficient data-hold time.
According to another aspect of the present invention, a semiconductor device includes an input buffer buffering an external clock signal to supply an internal clock signal, a timing-stabilization circuit which generates a phase-adjusted clock signal by adjusting a delay of a variable-delay circuit as the variable-delay circuit delays the internal clock signal, an overflow-detection circuit which generates an overflow-detection signal when the delay of the variable-delay circuit is set to an upper end of an adjustable delay range, and an output circuit which outputs the overflow-detection signal to an exterior of the semiconductor device.
The semiconductor device described above allows the overflow-detection signal to be output to the exterior of the semiconductor device, thereby making it possible to check outside the device as to whether overflow is present.
According to another aspect of the present invention, a semiconductor device includes an input buffer buffering an external clock signal to supply an internal clock signal, a timing-stabilization circuit which generates a phase-adjusted clock signal by adjusting a delay of a variable-delay circuit as the variable-delay circuit delays the internal clock signal, and an overflow-detection circuit which detects overflow when the delay of the variable-delay circuit is set to an upper end of an adjustable delay range, wherein the timing-stabilization circuit includes a feedback loop for controlling the delay of the variable-delay circuit, and a frequency divider which divides a frequency of the internal clock signal to generate a frequency-divided clock signal used in the feedback loop, wherein the frequency divider lowers a frequency of the frequency-divided clock signal when the overflow-detection circuit detects overflow.
In the semiconductor device described above, the frequency divider of the timing-stabilization circuit lowers the frequency of the frequency-divided clock signals when overflow is detected, thereby suppressing power consumption in the timing-stabilization circuit.
According to another aspect of the present invention, a semiconductor device includes an input buffer buffering an external clock signal to supply an internal clock signal, a timing-stabilization circuit which generates a phase-adjusted clock signal by adjusting a delay of a variable-delay circuit as the variable-delay circuit delays the internal clock signal, an overflow-detection circuit which detects overflow when the delay of the variable-delay circuit is set to an upper end of an adjustable delay range, and a circuit which stops supply of the internal clock circuit to the variable-delay circuit when the overflow-detection circuit detects overflow.
In the semiconductor device described above, supply of the internal clock signal to the variable-delay circuit is stopped when overflow is detected, thereby avoiding unnecessary power consumption in the variable-delay circuits.
According to another aspect of the present invention, a semiconductor device includes an input buffer buffering an external clock signal to supply an internal clock signal, a timing-stabilization circuit which generates a phase-adjusted clock signal by adjusting a delay of a rough-adjustment variable-delay circuit and a delay of a fine-adjustment variable-delay circuit as the rough-adjustment variable-delay circuit and the fine-adjustment variable-delay circuit delay the internal clock signal, and an overflow-detection circuit which detects overflow when the delay of the rough-adjustment variable-delay circuit is set to an upper end of an adjustable delay range.
In the semiconductor device described above, a delay adjustment is made by the rough-adjustment variable-delay circuit and the fine-adjustment variable-delay circuit in the timing-stabilization circuit, wherein overflow is detected when a delay of the rough-adjustment variable-delay circuit is set to the upper end of the adjustable delay range. An appropriate detection of overflow thus can be made.
According to another aspect of the present invention, a semiconductor device includes an input buffer buffering an external clock signal to supply an internal clock signal, a timing-stabilization circuit which generates a phase-adjusted clock signal by adjusting a delay of a variable-delay circuit as the variable-delay circuit delays the internal clock signal, an overflow-detection circuit which detects overflow when the delay of the variable-delay circuit is set to an upper end of an adjustable delay range, a selection circuit which supplies one of the internal clock signal and an inverse of the internal clock signal to an internal circuit as a substitute for the phase-adjusted clock signal serving as a synchronization signal in the internal circuit when the overflow-detection circuit detects overflow, and a control circuit which can override operations of the selection circuit based on at least one externally provided signal such that the at least one externally provided signal determines which clock signal is selected by the selection circuit regardless of whether the overflow-detection circuit detects overflow.
The semiconductor device described above is structured such that the internal clock signal or an inverse of the internal clock signal is selected as a synchronization signal in place of the phase-adjusted clock signal when overflow is detected, yet has the control circuit which can control the selection of the synchronization signal regardless of whether overflow is present. This configuration allows the semiconductor device to operate in synchronism with the phase-adjusted clock signal irrespective of presence of overflow and to undergo an operation test under this condition.
Other objects and further features of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings.